Thursday, April 27, 2017

Job: Intern (Technical-Engineering) at Synopsys Armenia CJSC Company

Location: 41 Arshakunyats Ave, Yerevan, 0026, Armenia

Category: Information Technology

Type: Internship

Deadline: 5/17/2017 12:00:00 AM

Salary: We offer competitive/ negotiable salary, + comprehensive medical insurance package for employee and his/ her family, including parents; Technical and English language trainings; comprehensive bonus plan, including Local Incentive plan

Description
Business Title Intern (Technical-Engineering)

Requisition Number 13630BR

Hiring Location(s) ARMENIA - Yerevan

Job Category Interns/Temp

Hire Type Intern


You will be part of a layout team developing physical layout of high speed analog integrated circuits. As mixed-signal layout engineer you will be exposed to SerDes PHY layout for PCIe, SATA, XAUI, and other protocols. As a designer of IP layout, circuits will be constructed so as to facilitate porting to multiple process nodes. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.
Developing professional expertise, applies company policies and procedures to resolve a variety of issues. Has working knowledge of work area and general proficiency with tools, systems, and procedures required to accomplish the job. Exercises judgment within defined procedures and practices to determine appropriate action. Receives general instructions on routine work, detailed instructions on new assignments. Implementations and solutions are reviewed for accuracy and overall adequacy. Builds productive internal/external working relationships. Contacts are primarily within business unit and occasional organizational and external customer contacts on routine matters.

Responsibilities
-Responsible for designing physical layout of custom analog and digital blocks for multi-Gb/s SERDES IP

RequiredQualifications
-In depth familiarity with layout of analog and mixed signal CMOS circuits
-Exposure to SERDES subcircuit layout (i.e. RX, TX, PLL, etc…)
-Design for porting (i.e. design so as to enable ease moving layout across multiple foundry nodes)
-Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding)
-Aware of layout techniques to mitigate ESD, latchup
-Familiarity with custom digital layout (i.e. high speed logic paths)
-Knowledge of design for reliability (i.e. EM, IR, etc…)
-Knowledge of layout effects (i.e. matching, reliability, proximity effects, etc…)
-Layout tool: Custom Designer (similar to Cadence)
-Verification tools: Hercules, ICV, Star-RCXT
-Exposure to scripting (i.e. TCL, PERL, etc…)

Benefits

Job URL: iJob.am - Intern (Technical-Engineering) @ Synopsys Armenia CJSC

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